1. Field of the Invention
The present invention relates to a shift register of a display device and a liquid crystal display (LCD) using the same, and more particularly, to a shift register generating a scanning signal for scanning gate lines in a gate line driving circuit of AMTFT-LCD (Active Matrix Thin Film Transistor Liquid Crystal Display) and for selecting a block of data lines in a data line block driving circuit.
2. Description of the Related Art
In these days, information processing devices have been rapidly developed in a trend with various architectures, functions and faster information processing speed. Information processed in these information processing devices has an electrical signal format. In order to visually confirm information processed in the information processing device, a display for a role as an interface should be provided.
LCDs have advantages such as the lighter weight, small size, high resolution, lower power consumption and friendly relation with environment and they render display of full colors compared with the traditional cathode ray tube (CRT). Such the advantages allow the LCDs to replace the CRTs and to be spotlighted as a next generation display.
LCDs apply an electric power to liquid crystal having a specific molecular configuration to vary the molecular arrangement of liquid crystal. The variation in the molecular configuration of liquid crystal causes a variation in optical properties such as birefringence, optical rotary power, dichroism and light scattering. The LCDs utilize such variations in optical properties to display an image.
The LCD device is largely sorted into a TN (Twisted Nematic) type and a STN (Super-Twisted Nematic) type. The liquid crystal display device is, according to the driving method, sorted into an active matrix display type, which uses a switching device and a TN liquid crystal, and a passive matrix type, which uses an STN liquid crystal.
A distinguishable difference of two types is in that the active matrix display type is applied to a TFT-LCD that drives the LCD by using a TFT and the passive matrix display type dispenses with a complicated circuit associated with a transistor because of using no transistor
TFT-LCD is divided into amorphous silicon TFT LCD (a-Si TFT-LCD) and polycrystalline silicon TFT LCD (poly-Si TFT-LCD). Poly-Si TFT-LCD has advantages of lower power consumption, lower price compared with a-Si TFT-LCD but has a drawback in that its manufacturing process is complicated. Thus, poly-Si TFT-LCD is mainly used in a small sized display such as mobile phones.
Amorphous-Si TFT-LCD is applied to a large screen sized display such as notebook personal computer (PC), LCD monitor, high definition (HD) television, etc., due to easy application of large screen and high production yield.
As shown in FIG. 1, poly-Si TFT LCD includes a data driving circuit 12 and a gate driving circuit 14 that are formed on a glass substrate 10 having a pixel array. A terminal part 16 is connected with an integrated printed circuit board (PCB) 20 using a film cable 18. This structure saves the manufacturing costs and minimizes the power loss due to the integration of driving circuits.
As shown in FIG. 2, amorphous-Si TFT LCD has a data driving chip 34 formed on a flexible printed circuit board 32 in a manner of COF (Chip-On-Film). A data printed circuit board 36 is connected with a data line terminal of the pixel array through the flexible PCB 32. A gate driving chip 40 is formed on a flexible PCB 38 in a manner of COF. A gate PCB 42 is connected with a gate line terminal through the flexible PCB 40.
Recently, there is also disclosed a technique for removing the gate PCB from the LCD by employing an integrated PCB technique mounting a gate power supply part on the data PCB. Korean Patent Laid-Open Publication No. 2000-66493 previously filed by the present assignee discloses an LCD module employing an integrated PCB by which the gate PCB is removed.
However, although the integrated PCB is employed, the flexible PCB having the flexible PCB is still used. Thus, since multiple flexible PCBs should be assembled in a glass substrate, a fabrication process of a-Si TFT LCD, especially OLB (Outer Lead Bonding) process becomes complicated compared with that of poly-Si TFT LCD, whereby its fabrication costs becomes higher.
Thus, there are many endeavors for decreasing the number of the assembly process by simultaneously forming data driving circuit and gate driving circuit along with pixel array on a glass substrate in a-Si TFT LCD like poly-Si TFT LCD.
U.S. Pat. No. 5,517,542 discloses a technique for an a-Si TFT gate driving circuit formed on a glass substrate.
In the above U.S. Pat. No. 5,517,542, a shift register of the gate driving circuit uses three clock signals. Each stage of the shift register two clock signals of three clock signals, is enabled with an output signal of previous stage as an input signal, and maintains the disable state by feed backing an output of the second next stage.
Each stage in the U.S. Patent provides a voltage applied to gate of full-down transistor in a capacitor charge manner in order to maintain the disable status. Thus, when an increase in gate threshold voltage of the full-down transistor due to stress of the full-down transistor is elevated higher than the charge voltage of the capacitor, there may occur a turn-off of the full-down transistor in the disable status.
The above U.S. patent employs a power supply circuit elevating a VDD in proportional to the increase in the threshold voltage of the a-Si TFT LCD in order to prevent an error operation due to the increase in the threshold voltage.
Accordingly, it is a first object of the present invention to provide a shift register making it possible to perform a stable operation regardless of the fluctuation in the threshold voltage of a-Si TFT LCD on a use of a long-term by maintaining an input node of the full-down means at a coupled status with the power voltage.
It is a second object of the present invention to provide an LCD capable of minimizing the number of external connection terminals on the LCD panel for the connection with an external circuit by using two clock signals.
It is a third object of the present invention to provide an amorphous silicon LCD in which a data driving circuit is integrated on a substrate.
It is a fourth object of the present invention to provide a method for operating gate lines of an LCD.
It is a fifth object of the present invention to provide a method for block-operating data lines of an LCD.
To accomplish the first object, there is provided a shift register in which multiple stages are connected one after another to each other, the multiple stages having a first stage in which a start signal being coupled to an input terminal, the shift register sequentially outputting output signals of respective stages. The multiple stages has odd stages for receiving a first clock signal and even stages for receiving a second clock signal having a phase opposite to the first clock signal.
Each of the multiple stages has: a pull-up means for providing a corresponding one of the first and second clock signals to an output terminal; a pull-up driving means connected to an input node of the pull-up means, for turning on the pull-up means in response to a front edge of an input signal and turning off the pull-up means in response to an output signal of a next stage; a pull-down means for providing a first power voltage to the output terminal; and a pull-down driving means connected to an input node of the pull-down means, for turning off the pull-down means in response to a front edge of the input signal and turning on the pull-down means in response to the front edge of the output signal of the next stage.
Here, the first power voltage is a turn off voltage (VOFF, VSS) and the second power voltage is a turn on voltage (VON, VDD).
Preferably, each stage further comprises a turn-on preventing means connected to the input node of the pull-down means, wherein the turn-on preventing means connects the first power voltage to the input node of the pull-down means in response to the output signal of the output terminal to prevent the pull-down means from being turned on.
The turn-on preventing means comprises an NMOS transistor of which drain is connected to the input node of the pull-down means, gate is connected to the output terminal and source is connected to the first power voltage.
Also, the pull-up driving means has a capacitor connected between the input node of the pull-up means and the output terminal; a first transistor of which drain and gate are commonly connected to the input terminal and source is connected to the input node of the pull-up means; a second transistor of which drain is connected to the input node of the pull-up means, gate is connected to the input node of the pull-down means and source is connected to the first power voltage; and a third transistor of which drain is connected to the input node of the pull-up means, gate is connected to an output signal of a next stage and source is connected to the first power voltage.
The pull-down driving means comprises: a fourth transistor of which drain is connected to the second power voltage, gate is connected to the output signal of the next stage and source is connected to the input node of the pull-down means; and a fifth transistor of which drain is connected to the input node of the pull-down means, gate is connected to the input signal and source is connected to the first power voltage.
The floating preventing means has a sixth transistor of which drain and gate are connected to the second power voltage and source is connected to the input node of the pull-down means, wherein the sixth transistor has a size smaller sufficiently than the fifth transistor. Here, it is preferable that a size ratio of the fifth transistor to the sixth transistor is approximately 20:1.
By the above constitution, it is desirable that the external connection terminal connected to the shift register comprises five terminals of a first clock signal input terminal, a second clock signal input terminal, a start signal input terminal, a first power voltage input terminal and a second power voltage input terminal.
Also, it is desirable that a size ratio of the fifth transistor to the seventh transistor is approximately 2:1.
To achieve the first object, there is provided a shift register according to another aspect of the present invention. The shift register includes multiple stages connected in cascade fashion. The multiple stages have a first stage in which a start signal is coupled to an input terminal. The shift register sequentially outputs output signals of the respective stages. The multiple stages have odd stages for receiving a first clock signal and a second clock signal having a phase opposite to the first clock signal at a first clock terminal and a second clock terminal of the odd stages, and even stages for receiving the second clock signal and the first clock signal at a first clock termianl and a second clock terminal of the even stages.
Each of the multiple stages comprises: an input terminal connected to an output terminal of a previous stage; an output terminal connected to a corresponding gate line; a first control terminal connected to a second control terminal of a stage after the next stage; a second control terminal; a clock terminal into which a corresponding clock signal is inputted; a pull-up means for providing a corresponding one out of the first and second clock signals to the output terminal; a pull-down means for providing a first power voltage to the output terminal; a pull-up driving means connected to an input node of the pull-up means, for turning on the pull-up means in response to a front edge of an input signal and turning off the pull-up means in response to a front edge of a control signal supplied to the control terminal; and a pull-down driving means connected to an input node of the pull-down means and an input node of the pull-up means, for turning off the pull-down means, and for turning on the pull-down means in response to a front edge of an output signal of the next stage.
Here, the pull-up driving means comprises: a capacitor connected between the input node of the pull-up means and the output terminal; a first transistor of which drain and gate are commonly connected to the input signal and source is connected to the input node of the pull-up means; and a second transistor of which drain is connected to the input node of the pull-up means, gate is connected to the output signal of the next stage and source is connected to the first power voltage.
Preferably, the first transistor receives the start signal or the input signal from the previous stage through the commonly connected gate and drain, and charges the capacitor through the capacitor.
Also, the pull-up driving means discharges the control signal of the pull-up means using a pull-up control signal provided from the second control terminal.
Further, the pull-down driving means comprises: a third transistor of which drain is connected to the first power voltage, gate is connected to the output signal of the next stage and source is connected to the input node of the pull-down means; and a fourth transistor of which drain and gate are commonly connected to the second clock signal and source is connected to the input node of the pull-down means.
To achieve the first object of the present invention, there is provided a shift register according to further another aspect of the invention. The shift register includes multiple stages connected in cascade fashion. The multiple stages having a first stage in which a start signal is coupled to an input terminal. The shift register sequentially outputs output signals of the respective stages. The multiple stages include odd stages for receiving a first clock signal and a second clock signal having a phase opposite to the first clock signal.
Each of the multiple stages comprises: a, pull-up means for providing a corresponding one out of the first and second clock signals; a pull-down means for providing a first power voltage to the output terminal; a pull-down driving means connected to an input node of the pull-down means, for turning off the pull-down means in response to a front edge of the input signal and turning on the pull-down means in response to a front edge of an output signal of a next stage; and a pull-up driving means provided with a capacitor of which one end is connected to an input node of the pull-up means and the other end is connected to the output terminal, and a discharging means for forcibly discharging the capacitor depending on an external input control signal, the pull-up driving means turning on the pull-up means by charging the capacitor in response to the front edge of the input signal and turning off the pull-up means by forcibly discharging the capacitor in response to the front edge of the output signal of the next stage.
Here, the pull-up driving means comprises: a capacitor connected between the input node of the pull-up means and the output terminal; a first transistor of which gate is connected to the input signal, drain is connected to a second power voltage and source is connected to the input node of the pull-up means; a second transistor of which drain is connected to the input node of the pull-up means, gate is connected to the input node of the pull-down means and source is connected to the first power voltage; a third transistor of which drain is connected to the input node of the pull-up means, gate is connected to the output signal of the next stage and source is connected to the first power voltage; and a fourth transistor of which drain is connected to the input node of the pull-up means, source is connected to the first power voltage and gate forcibly discharges the capacitor which receives the external input control signal.
Preferably, the external input control signal has a voltage level capable of turning on the transistor when a power is applied and turning off the transistor before the start signal is applied to the first stage. Also, the external input control signal has a voltage level capable of turning off the transistor while the start signal is applied to the first stage and an output of a last shift register is generated, and turning on the transistor after the output of the last shift register is generated, thereby discharging the capacitor of the last shift register.
Further, the pull-up driving means comprises: a capacitor connected between the input node of the pull-up means and the output terminal; a first transistor of which gate is connected to the input signal, drain is connected to a second power voltage and source is connected to the input node of the pull-up means; a second transistor of which drain is connected to the input node of the pull-up means, gate is connected to the input node of the pull-down means and source is connected to the first power voltage; and a third transistor of which drain is connected to the input node of the pull-up means, gate is connected to the output signal of the next stage and source receives the external input control signal to forcibly discharge the capacitor.
The sources of the second transistor and the third transistor are commonly connected to each other. The external input control signal maintains a low state simultaneously with an application of a power to thereby forcibly discharge the capacitor, and maintains a high state before the start signal applied to the first stage is generated.
Furthermore, the external input control signal has a voltage level capable of turning on the third transistor when a power is applied, and turning off the third transistor before the start signal is applied to the first stage. The turning on voltage level is the second power voltage, and the turning off voltage level is the first power voltage.
Moreover, the second power voltage is above a threshold voltage capable of turning on the third transistor even when the first power voltage is applied to the gate terminal of the third transistor and less than the first power voltage. The external input control signal has a voltage level capable of turning off the transistor while the start signal is applied to the first stage and an output of a last shift register is generated, and turning on the transistor after the output of the last shift register is generated, thereby discharging the charge accumulated in the capacitor of the last shift register.
To accomplish the second and third objects of the present invention, there is an LCD comprising a display cell array circuit, a data driving circuit and a gate driving circuit formed on a transparent substrate.
The display cell array circuit has multiple data lines and multiple gate lines, each of the display cell arrays connected to a corresponding pair of data line and gate line.
The gate driving circuit has a first shift register comprising multiple stages connected one after another to each other, the multiple stages having a first stage in which a start signal is coupled to an input terminal, for sequentially selecting the multiple gate lines using an output signal of each stage.
The data driving circuit comprising multiple data line blocks and a second shift register, each of the data line blocks comprising multiple driving transistors each of which drain and source are connected between a data input terminal and the data line and gate is commonly connected to a block selection terminal, the second shift register comprising multiple stages connected one after another to each other, the multiple stages having a first stage in which a data block selection start signal is coupled to an input terminal, for sequentially selecting the multiple data line blocks using an output signal of each stage.
The LCD further comprises a flexible PCB on which an integral control and data driving chip is mounted, for providing the input terminals of the gate and data driving circuits with a control signal and a data signal.
The first and second shift registers employ the shift register for accomplishing the first object of the present.
It is desirable that a duty period of the first and second clock signals applied to the first shift register is greater than a period of a duty period of the first and second clock signals applied to the second shift register multiplied by a number of the data line blocks.
The transparent substrate is connected to the flexible PCB through an external connection terminal. The external connection terminal has; five terminals connected to the data driving circuit of a first clock signal input terminal, second clock signal input terminal, scan start signal input terminal, first power voltage input terminal and second power voltage input terminal; and three control terminals of first clock signal input terminal, second clock signal input terminal and block selection start signal input terminal; and multiple data input terminals all of which are connected to the data driving circuit.
To accomplish the fourth object of the present invention, there is provided a method for driving gate lines in the above LCD. In the above method, a capacitor is charged using an input signal to pull-up a gate line connected to the output terminal during a one-duty period of the clock signals. The pull-up state is maintained using the output signal of the output terminal. The pulling-down of the gate line and discharge of the capacitor are started in response to a rear edge of the output signal. The gate line is completely pulled-down in response to an output signal of a next stage. The pull-down state is maintained using a second power voltage that is always provided to the input node of the pull-down means.
Also, there is provided a method for driving gate lines in the above LCD. The method drives the multiple gate lines using the shift register having the multiple stages in response to the start signal.
In the above method, odd gate lines are driven by sampling a first clock signal using odd stages of the shift register for odd gate lines and driving the odd gate lines during an one-duty period of the sampled first clock signal and even gate lines are driven by sampling a second clock signal having an opposite phase to the first clock signal using even stages of the shift register for even gate lines and driving the even gate lines during an 1 duty period of the sampled second clock signal. Also, the sampling of each stage is initiated in response to an output signal of a previous stage and is ended in response to an output signal of a next stage.
To accomplish the fifth object of the present invention, there is provided a method for block-driving data lines in the above LCD. In the above method, a capacitor is charged using an input signal to enable a data line block connected to the output terminal during an 1 duty period of the clock signals. The enable state is maintained using the output signal of the output terminal. It is started to disable the data line block and discharge the capacitor in response to a rear edge of the output signal. The data line block is completely disabled in response to an output signal of a next stage. The disable state is maintained using a second power voltage that is provided to the input node of the pull-down means.
Also, there is provided a method for block-driving data lines in the above LCD. In the above method, the multiple gate lines are sequentially driven using the shift register having the multiple stages in response to the block selection start signal, in which odd gate lines are driven by sequentially sampling a first clock signal using odd stages of the shift register and driving the odd gate line blocks during an 1 duty period of the sampled first clock signal and even gate lines are driven by sampling a second clock signal having an opposite phase to the first clock signal and driving the even data line blocks during an 1 duty period of the sampled second clock signal, in which the sampling of each stage is initiated in response to an output signal of a previous stage and is ended in response to an output signal of a next stage.